FPGAs and DPGAs, and similar systems with two- or multi-dimensional programmable cell architectures, have internal bus systems which either have a global connection to all or most of the logic cells or have a local next-neighbor connection. Both types have in common the fact that they involve connections between two or more logic cells. In addition, always exactly one signal can use the bus, unless a multiplexer architecture is configured together with a control into a plurality of logic cells.
According to German Patent No. DE 44 16 881, the bus systems described above already exist in DFP-based systems. In addition, there is the possibility of separating a bus system, thus resulting in several sub-buses that can be used separately.
In German Application No. DE 196 54 595.1-53, an I/O bus system is described which combines a plurality of bus systems within the unit, where a unit may be an FPGA, a DPGA, a DFP, etc., and leads out of the unit. Memory modules or peripheral devices or other units of the generic type mentioned above can be triggered in this way. There is only one address register or address counter to generate the external addresses.
Conventional bus systems are not suitable for transmitting large volumes of data in the form of signals grouped by bytes or otherwise. Especially when the units are used for computation of algorithms, it is necessary for a plurality of data (packets) to be transmitted simultaneously between the individual configured function areas of a unit. In the usual technology, a direct point-to-point connection must be set up for each data path, which is the connection (the bus) between two (or more) function blocks that receive the same data, and which then regulates the data traffic between these function blocks exclusively. There can be only one data packet on the bus at a time. The interconnection complexity is very high. The transmission rate of today""s internal buses is limited by the maximum bus size and the signal propagation time on the bus. With the I/O bus described in German Application No. DE 196 54 595.1-53, only one type of bus connection can be set up per I/O cell, namely exclusively that programmed in the address register. There is no possibility of responding to different types of data or data transmitters and connecting them to different external units.
An object of the present invention is to create a bus system that can transmit data between a plurality of function blocks, where multiple data packets can be on the bus at the same time. The bus system automatically recognizes the correct connection for various types of data or data transmitters and sets it up.